1. Field of the Invention
The present invention relates to a method for controlling a sense amplifier of a memory device, and more particularly, to a method and circuit for automatically controlling an operation of a sense amplifier in correspondence with variations of operating voltage and frequency of a memory device.
2. Description of the Related Art
FIG. 1 is a diagram illustrating a read and write operations in a general memory device.
As shown in FIG. 1, during a write operation, data applied through an input/output data pad is transferred to a bitline sense amplifier through a data input buffer and a data input register. While, during a read operation, cell data amplified by the bitline sense amplifier is transferred to the input/output data pad through a data sense amplifier, a pipe register, and a data output buffer.
In FIG. 1, signal Yi is a pulse signal to connect the bitline sense amplifier with the data sense amplifier so as to control an operation of a data bus. While the signal Yi controlling the data bus is being enabled, the write data is transferred to the bitline sense amplifier from a write driver and the read data is transferred to the data sense amplifier from the bitline sense amplifier. It is advantageous to make a pulse width of the signal Yi wider in transferring valid data in an active operation mode (the read or write operation). It is also efficient to improve the performance of tDPL (a time from when a CAS pulse signal is generated internally by a write command to when a precharge pulse signal is generated internally by a precharge command) because the time parameter tDPL contributes to making restoring facilities of data better. Therefore, it is usual to establish the pulse width of the signal Yi as wider as possible within the permissible range and to use it with shrinking down in accordance with operational conditions. In reference, as an operating frequency of a memory device increases (i.e., a clock cycle period is shorter), a permissible pulse width of the signal Yi becomes narrower.
Meanwhile, as the signal Yi is made from responding to a read/write strobe pulse signal rdwtatbzp13 output from a read/write strobe pulse generator, hereinafter will be explained about the read/write strobe pulse generator.
FIG. 2A illustrates an example of a conventional read/write strobe pulse generator and FIG. 2B is a waveform diagram of signals used in the circuit shown in FIG. 2A.
In FIG. 2A, signals extyp8 and icasp6 are signals to make a data transmission line short or open, so as to read data to a peripheral circuit from a cell array of the memory device or to write data in the cell array of the memory device from a peripheral circuit. For information, it's named a core section for the range including a memory cell and a bitline sense amplifier and the rest a peripheral circuit.
In detail, the signal extyp8 is a pulse signal that is generated in sync with a clock signal when a read or write command (burst command) is applied to the memory device. And, the signal icasp6 is a signal to be used in operating the memory device by generating a self-burst operation command that is established with a burst length set by an MRS (mode register set) mode from a clock time later by one clock cycle period than a clock time when a read or write command is applied from the external.
The signal rdwtstbzp13 is a signal to be active for the burst length set by the MRS mode, being activated in sync with the signals of the burst operation command (external=exryp8 & internal=icasp61). In other words, the signal rdwtstbzp13 is to be used to inform an activation time of the input/output sense amplifier in amplifying and transferring data, which is to be sent to a peripheral circuit from a core circuit region, to the data output buffer, resetting the data transmission line of the peripheral circuit after completing the data amplification and transmission by the sense amplifier.
A signal pwrup is a signal to set an initial data value, retaining low level after falling down to low level from high level. Signal term_z is a signal used in a test mode being held on low level during a normal operation. A signal tm_clkpulsez is used in a test mode. Such signals will be described in detail in conjunction with embodiments of the present invention hereinafter.
A circuit operation of FIG. 2A is illustrated, as follows, with reference to the waveform diagram of FIG. 2B.
As illustrated in FIG. 2B, when the read/write command is applied to the memory device in sync with the clock signal clock, the pulse signal extyp8 is generated. If the pulse signal extyp8 is enabled, a plurality of pulse signals icasp6 is generated in sync with the next clocks in sequence. As shown in FIG. 2B, the read/write strobe pulse signal rdwtstbzp13 is generated in sync with rising edges of the pulse signals extyp8 and icasp6.
Here, in the conventional circuit shown in FIG. 2A, it can be seen that the pulse width of the read/write strobe pulse signal rdwtstbzp13 generated from a pulse width adjusting circuit 200 is fixed nevertheless of the operating frequency of the memory device. Here, a delay time from a node A from a node D is determined by a delay circuit 20. As the delay time of the delay circuit 20 in the pulse width adjusting circuit 200 is fixed, the pulse width of the signal outputted from the pulse width adjusting circuit 200 is always constant without regarding to the operating frequency of the memory device.
But, it needs to adjust a pulse width of the read/write strobe pulse signal rdwtstbzp13 when an operating frequency of the memory device varies. In a conventional art, while the delay time of the delay circuit 20 is variable by modifying a metal option during a FIB process when an operating frequency of the memory device varies, it needs much costs and times.
In addition, with the conventional art, there is no way to correct a variation of the pulse width of the read/write strobe pulse signal rdwtstbzp13 when an operation voltage of the memory device varies.